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1 for more information www.linear.com/ltc2152-12 typical application features applications description single 12-bit 250msps/ 210msps/170msps adcs n communications n cellular basestations n software defned radios n medical imaging n high defnition video n testing and measurement instruments n 68.5db snr n 90db sfdr n low power: 347mw/333mw/306mw total n single 1.8v supply n ddr lvds outputs n easy-to-drive 1.5v p-p input range n 1.25ghz full power bandwidth s/h n optional clock duty cycle stabilizer n low power sleep and nap modes n serial spi port for confguration n pin-compatible 14-bit versions n 40-lead (6mm 6mm) qfn package the lt c ? 2152-12/ltc2151-12/ltc2150-12 are a family of 250msps/210msps/170msps 12- bit a/d converters designed for digitizing high frequency, wide dynamic range signals. they are perfect for demanding communications applications with ac performance that includes 68.5db snr and 90 db spurious free dynamic range ( sfdr). the 1.25ghz input bandwidth allows the adc to undersample high input frequencies with good performance. the latency is only six clock cycles. dc specs include 0.26lsb inl ( typ), 0.16lsb dnl ( typ) and no missing codes over temperature. the transition noise is 0.54lsb rms . the digital outputs are double-data rate (ddr) lvds. the enc + and enc C inputs can be driven differentially with a sine wave, pecl, lvds, ttl , or cmos inputs. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. ltc2152-12: 32k point 2-tone fft , f in = 71mhz and 69mhz, 250msps frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 ta01b 100 120 ?20 s/h correction logic output drivers 12-bit pipelined adc clock/duty cycle control d10_11 ? ? ? d0_1 clock analog input 21521012 ta01a ddr lvds v dd gnd ov dd ognd 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
2 for more information www.linear.com/ltc2152-12 absolute maximum ratings supply voltage v dd , ov dd ................................................ C0. 3 v to 2v analog input voltage a in + , a in C , par / ser , sense ( no te 3) ........................ C 0.3 v to (v dd + 0.2 v) digital input voltage enc + , enc C ( note 3) ................ C0. 3 v to (v dd + 0.3 v) cs , sdi , sck ( note 4) ........................... C 0.3 v to 3.9 v sdo ( note 4) ............................................. C 0.3 v to 3.9 v digital output voltage ................ C 0.3 v to ( ov dd + 0.3 v) operating temperature range ltc 2 152 c , ltc 2151 c, ltc 2150 c ............. 0 c to 70 c ltc 2 152 i, ltc 2151 i, ltc 2150 i ............ C 40 c to 85 c storage temperature range .................. C 65 c to 150 c (notes 1, 2) pin configuration 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 top view gnd 41 uj package 40-lead (6mm 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 v dd v dd gnd a in + a in ? gnd sense vref vcm gnd ov dd d6_7 + d6_7 ? clkout + clkout ? d4_5 + d4_5 ? d2_3 + d2_3 ? ognd par/ser cs sck sdi sdo gnd d10_11 + d10_11 ? d8_9 + d8_9 ? enc + enc ? gnd of ? of + nc nc d0_1 ? d0_1 + ov dd 21 30 10 1 t jmax = 150c, ja = 33c/w exposed pad ( pin 41) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range ltc2152cuj-12#pbf ltc2152cuj-12#trpbf ltc2152uj-12 40-lead (6mm 6mm) plastic qfn 0c to 70c ltc2152iuj-12#pbf ltc2152iuj-12#trpbf ltc2152uj-12 40-lead (6mm 6mm) plastic qfn C40c to 85c ltc2151cuj-12#pbf ltc2151cuj-12#trpbf ltc2151uj-12 40-lead (6mm 6mm) plastic qfn 0c to 70c ltc2151iuj-12#pbf ltc2151iuj-12#trpbf ltc2151uj-12 40-lead (6mm 6mm) plastic qfn C40c to 85c ltc2150cuj-12#pbf ltc2150cuj-12#trpbf ltc2150uj-12 40-lead (6mm 6mm) plastic qfn 0c to 70c ltc2150iuj-12#pbf ltc2150iuj-12#trpbf ltc2150uj-12 40-lead (6mm 6mm) plastic qfn C40c to 85c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
3 for more information www.linear.com/ltc2152-12 converter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions ltc2152-12 ltc2151-12 ltc2150-12 units min typ max min typ max min typ max resolution ( no missing codes) l 12 12 12 bits integral linearity error differential analog input (note 6) l C1.2 0.26 1.2 C1.2 0.30 1.2 C1.2 0.30 1.2 lsb differential linearity error differential analog input l C0.6 0.16 0.6 C0.6 0.16 0.6 C0.6 0.16 0.6 lsb offset error (note 7) l C13 5 13 C13 5 13 C13 5 13 mv gain error external reference l C4 1 3 C4 1 3 C4 1 3 %fs offset drift 20 20 20 v/c full-scale drift internal reference external reference 30 10 30 10 30 10 ppm /c ppm/c transition noise 0.54 0.54 0.54 lsb rms analog input the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1.5 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l v cm C 20mv v cm v cm + 20mv v v sense external reference mode external reference mode l 1.200 1.250 1.300 v i in1 analog input leakage current 0 < a in + , a in C < v dd , no encode l C1 1 a i in2 sense input leakage current 1.2v < sense < 1.3v l C1 1 a i in3 par /ser input leakage current 0 < par /ser < v dd l C1 1 a t ap sample-and-hold acquisition delay time 1 ns t jitter sample-and-hold acquisition delay jitter 0.15 ps rms cmrr analog input common mode rejection ratio 75 db bw-3b full-power bandwidth 1250 mhz dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. a in = C1dbfs. (note 5) symbol parameter conditions ltc2152-12 ltc2151-12 ltc2150-12 units min typ max min typ max min typ max snr signal-to-noise ratio 15mhz input 70mhz input 140mhz input l 67.1 68.5 68.4 68.0 67.1 68.5 68.3 67.9 67.3 68.5 68.3 67.8 dbfs dbfs dbfs sfdr spurious free dynamic range 2nd or 3rd harmonic 15mhz input 70mhz input 140mhz input l 72 90.6 88 80 74 90.1 89 81 76 90 88 80 dbfs dbfs dbfs spurious free dynamic range 4th harmonic or higher 15mhz input 70mhz input 140mhz input l 81 98 95 85 82 98 95 85 83 98 95 84 dbfs dbfs dbfs s /(n+d) signal-to-noise plus distortion ratio 15mhz input 70mhz input 140mhz input l 66.5 68.5 68.4 67.7 66.6 68.4 68.3 67.7 66.7 68.4 68.3 67.7 dbfs dbfs dbfs crosstalk crosstalk between channels up to 315mhz input C95 C95 C95 db 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
4 for more information www.linear.com/ltc2152-12 internal reference characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.439 ? v dd C 18mv 0.439 ? v dd 0.439 ? v dd + 18mv v v cm output temperature drift 37 ppm/c v cm output resistance C1ma < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 30 ppm/c v ref output resistance C400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage (note 8) l 0.2 1 1.9 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1.2 1.5 v v v in input voltage range enc + , enc C to gnd l 0.2 1.9 v r in input resistance (see figure 2) 10 k c in input capacitance (note 8) 2 pf digital inputs ( cs, sdi, sck) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 1.8v l C10 10 a c in input capacitance (note 8) 3 pf sdo output (open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v, sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C10 10 a c out output capacitance (note 8) 4 pf power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions ltc2152-12 ltc2151-12 ltc2150-12 units min typ max min typ max min typ max v dd analog supply voltage (note 9) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v ov dd output supply voltage lvds mode (note 9) l 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 v i vdd analog supply current l 166 185 158 175 145 159 ma i ovdd digital supply current 1.75ma lvds mode 3.5ma lvds mode l 27 45 32 50 27 44 31 50 25 43 30 48 ma ma p diss power dissipation 1.75ma lvds mode 3.5ma lvds mode l 347 380 391 423 333 364 371 405 306 338 340 373 mw mw p nap nap mode power clocked at f s(max) 105 99 93 mw p sleep sleep mode power clocked at f s(max) <2 <2 <2 mw ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
5 for more information www.linear.com/ltc2152-12 symbol parameter conditions min typ max units digital d ata outputs v od differential output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 247 125 350 175 454 250 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 differential load, 1.75ma mode l l 1.125 1.125 1.250 1.250 1.375 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 5) symbol parameter conditions ltc2152-12 ltc2151-12 ltc2150-12 units min typ max min typ max min typ max f s sampling frequency (note 9) l 10 250 10 210 10 170 mhz t l enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 1.9 1.5 2 2 50 50 2.26 1.5 2.38 2.38 50 50 2.79 1.5 2.94 2.94 50 50 ns ns t h enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 1.9 1.5 2 2 50 50 2.26 1.5 2.38 2.38 50 50 2.79 1.5 2.94 2.94 50 50 ns ns digital d ata outputs ltc215x-12 symbol parameter conditions min typ max units t d enc to data delay c l = 5pf l 1.7 2 2.3 ns t c enc to clkout delay c l = 5pf l 1.3 1.6 2 ns t skew data to clkout skew t d C t c l 0.3 0.4 0.55 ns pipeline latency 6 6 cycles spi port timing (note 8) t sck sck period write mode, c sdo = 20pf readback mode r pullup = 2k, c sdo = 20pf 40 250 ns ns t s cs to sck set-up time l 5 ns t h sck to cs hold time l 5 ns t ds sdi set-up time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid readback mode r pullup = 2k, c sdo = 20pf l 125 ns note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd with gnd and ognd shorted (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v, f sample = 250mhz (ltc2152), 210mhz (ltc2151), or 170mhz (ltc2150), lvds outputs, differential enc + /enc C = 2v p-p sine wave, input range = 1.5v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5lsb when the output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2s complement output mode. note 8: guaranteed by design, not subject to test. note 9: recommended operating conditions. 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
6 for more information www.linear.com/ltc2152-12 typical performance characteristics ltc2152-12: integral nonlinearity (inl) ltc2152-12: differential nonlinearity (dnl) ltc2152-12: 32k point fft , f in = 15mhz, C1dbfs, 250msps ltc2152-12: 32k point fft , f in = 70mhz, C1dbfs, 250msps ltc2152-12: 32k point fft , f in = 122mhz, C1dbfs, 250msps ltc2152-12: 32k point fft , f in = 380mhz, C1dbfs, 250msps ltc2152-12: 32k point fft , f in = 420mhz, C1dbfs, 250msps ltc2152-12: 32k point fft , f in = 229mhz, C1dbfs, 250msps ltc2152-12: 32k point fft , f in = 171mhz, C1dbfs, 250msps output code 0 ?2.0 ?1.5 ?1.0 ?0.5 inl error (lsb) 0 0.5 2.0 1.5 1.0 4095 21521012 g01 output code 0 ?0.50 ?0.25 dnl error (lsb) 0 0.25 0.50 4095 21521012 g02 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g03 100 120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g04 100 120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g05 100 120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g06 100 120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g07 100 120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g08 100 120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g09 100 120 ?20 ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
7 for more information www.linear.com/ltc2152-12 ltc2152-12: 32k point fft , f in = 907mhz, C1dbfs, 250msps ltc2152-12: 32k point 2-tone fft , f in = 71mhz and 69mhz, 250msps ltc2152-12: shorted input histogram ltc2152-12: i ovdd vs sample rate, 15mhz sine wave input, C1dbfs ltc2152-12: i vdd vs sample rate, 15mhz sine wave input, C1dbfs ltc2152-12: 32k point fft , f in = 567mhz, C1dbfs, 250msps typical performance characteristics ltc2152-12: sfdr vs input level, f in = 70mhz, 1.5v range, 250msps frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 215210 g10 100 120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g11 100 120 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g12 100 120 ?20 output code 2048 count 12000 16000 20000 21521012 g13 8000 4000 10000 14000 18000 6000 2000 0 2052 2056 sample rate (msps) 0 i ovdd (ma) 35 45 40 50 200 21521012 g14 30 25 15 20 50 100 150 250 lvds current 3.5ma lvds current 1.75ma sample rate (msps) 0 i vdd (ma) 140 150 160 170 200 21521012 g15 130 120 110 50 100 150 250 amplitude (dbfs) ?90 0 sfdr (dbfs) 40 20 80 100 120 ?70 ?50 ?40 0 21521012 g16 60 ?80 ?60 ?30 ?20 ?10 dbfs dbc ltc2152-12: sfdr vs input frequency, C1dbfs, 1.5v range, 250msps ltc2152-12: snr vs input level, f in = 70mhz, 1.5v range, 250msps input level (dbfs) 10 0 snr (dbc and dbfs) 20 30 40 50 70 60 ?70 ?50 ?30 ?60 ?40 ?20 ?10 0 21521012 g17 dbfs dbc input frequency (mhz) 0 sfdr (dbfs) 50 40 60 70 800 21521012 g18 20 30 10 0 200 400 500 1000 90 80 600 100 300 900 700 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
8 for more information www.linear.com/ltc2152-12 typical performance characteristics ltc2152-12: frequency response ltc2151-12: integral nonlinearity inl ltc2151-12: differential nonlinearity dnl ltc2151-12: 32k point fft , f in = 15mhz, C1dbfs, 210msps ltc2151-12: 32k point fft , f in = 71mhz, C1dbfs, 210msps ltc2151-12: 32k point fft , f in = 101mhz, C1dbfs, 210msps ltc2152-12: snr vs input frequency, C1dbfs, 1.5v range, 250msps ltc2151-12: 32k point fft , f in = 171mhz, C1dbfs, 210msps input frequency (mhz) 0 snr (dbfs) 55 50 60 65 800 21521012 g19 45 40 200 400 500 1000 75 70 600 100 300 900 700 input frequency (mhz) ?5.0 input amplitude (dbfs) ?4.5 ?3.5 ?3.0 ?2.5 1000 ?0.5 21521012 g20 ?4.0 100 ?2.0 ?1.5 ?1.0 output code 0 ?2.0 ?1.5 ?1.0 ?0.5 inl error (lsb) 0 0.5 2.0 1.5 1.0 4095 21521012 g21 output code 0 ?0.50 ?0.25 dnl error (lsb) 0 0.25 0.50 4095 21521012 g22 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g23 100 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g24 100 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g25 100 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g26 100 ?20 ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
9 for more information www.linear.com/ltc2152-12 ltc2151-12: 32k point fft , f in = 227mhz, C1dbfs, 210msps ltc2151-12: 32k point fft , f in = 379mhz, C1dbfs, 210msps typical performance characteristics frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g27 100 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g28 100 ?20 ltc2151-12: 32k point fft , f in = 567mhz, C1dbfs, 210msps ltc2151-12: 32k point fft , f in = 907mhz, C1dbfs, 210msps ltc2151-12: 32k point 2-tone fft , f in = 71mhz and 69mhz, 210msps ltc2151-12: shorted input histogram ltc2151-12: 32k point fft , f in = 417mhz, C1dbfs, 210msps ltc2151-12: i ovdd vs sample rate, 15mhz sine wave input, C1dbfs frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g29 100 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g30 100 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 g31 100 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 100 21521012 g32 ?20 output code 2044 2048 count 12000 16000 20000 21521012 g33 8000 4000 10000 14000 18000 6000 2000 0 2052 2056 sample rate (msps) 0 i ovdd (ma) 40 45 50 168 21521012 g34 30 35 20 25 15 42 84 128 210 lvds current 3.5ma lvds current 1.75ma ltc2151-12: i vdd vs sample rate, 15mhz sine wave input, C1dbfs sample rate (msps) 0 i vdd (ma) 150 160 168 21521012 g35 140 130 120 110 42 84 126 210 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
10 for more information www.linear.com/ltc2152-12 typical performance characteristics ltc2151-12: snr vs input level, C1dbfs, 1.5v range, 210msps ltc2151-12: frequency response ltc2151-12: snr vs input level, f in = 70mhz, 1.5v range, 210msps ltc2151-12: sfdr vs input level, C1dbfs, 1.5v range, 210msps ltc2151-12: sfdr vs input level, f in = 70mhz, 1.5v range, 210msps amplitude (dbfs) 0 sfdr (dbfs) 40 20 80 100 120 ?70 ?50 ?40 0 21521012 g36 60 ?80 ?60 ?30 ?20 ?10 10 dbfs dbc input level (dbfs) 10 0 snr (dbc and dbfs) 20 30 40 50 70 60 ?70 ?50 ?30 ?60 ?40 ?20 ?10 0 21521012 g37 dbfs dbc input frequency (mhz) 0 sfdr (dbfs) 50 40 60 70 800 21521012 g38 20 30 10 0 200 400 500 1000 90 80 600 100 300 900 700 ltc2150-12: 32k point fft , f in = 15mhz, C1dbfs, 170msps ltc2150-12: integral nonlinearity inl ltc2150-12: differential nonlinearity dnl input frequency (mhz) 0 snr (dbfs) 55 50 60 65 800 21521012 g39 45 40 200 400 500 1000 75 70 600 100 300 900 700 input frequency (mhz) ?5.0 input amplitude (dbfs) ?4.5 ?3.5 ?3.0 ?2.5 1000 ?0.5 21521012 g40 ?4.0 100 ?2.0 ?1.5 ?1.0 output code 0 ?2.0 ?1.5 ?1.0 ?0.5 inl error (lsb) 0 0.5 2.0 1.5 1.0 4095 21521012 g41 output code 0 ?0.50 ?0.25 dnl error (lsb) 0 0.25 0.50 4095 21521012 g42 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 10 30 50 70 21521012 g43 80 ?20 ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
11 for more information www.linear.com/ltc2152-12 typical performance characteristics ltc2150-12: 32k point fft , f in = 121mhz, C1dbfs, 170msps ltc2150-12: 32k point fft , f in = 176mhz, C1dbfs, 170msps ltc2150-12: 32k point fft , f in = 225mhz, C1dbfs, 170msps ltc2150-12: 32k point fft , f in = 70mhz, C1dbfs, 170msps frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 10 30 50 70 21521012 g44 80 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 10 30 50 70 21521012 g45 80 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 10 30 50 70 21521012 g46 80 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 10 30 50 70 21521012 g47 80 ?20 ltc2150-12: 32k point fft , f in = 380mhz, C1dbfs, 170msps ltc2150-12: 32k point fft , f in = 420mhz, C1dbfs, 170msps ltc2150-12: 32k point fft , f in = 567mhz, C1dbfs, 170msps ltc2150-12: 32k point fft , f in = 907mhz, C1dbfs, 170msps ltc2150-12: 32k point 2-tone fft , f in = 71mhz and 69mhz, 170msps frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 10 30 50 70 21521012 g48 80 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 10 30 50 70 21521012 g49 80 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 10 30 50 70 21521012 g50 80 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 10 30 50 70 21521012 g51 80 ?20 frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 30 10 40 50 60 70 80 21521012 g52 ?20 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
12 for more information www.linear.com/ltc2152-12 ltc2150-12: i ovdd vs sample rate, 15mhz sine wave input, C1dbfs ltc2150-12: i vdd vs sample rate, 15mhz sine wave input, C1dbfs ltc2150-12: shorted input histogram typical performance characteristics ltc2150-12: snr vs input level, f in = 70mhz, 1.5v range, 170msps ltc2150-12: sfdr vs input frequency, C1dbfs, 1.5v range, 170msps ltc2150-12: snr vs input frequency, C1dbfs, 1.5v range, 170msps ltc2150-12: frequency response ltc2150-12: sfdr vs input level, f in = 70mhz, 1.5v range, 170msps output code 2056 count 12000 16000 20000 21521012 g53 8000 4000 10000 14000 18000 6000 2000 0 2060 2064 sample rate (msps) 0 15 i ovdd (ma) 20 30 35 40 68 136 170 60 21521012 g54 25 34 102 45 50 55 lvds current 3.5ma lvds current 1.75ma sample rate (msps) 0 i vdd (ma) 135 140 136 21521012 g55 130 125 120 115 110 105 100 34 68 102 170 amplitude (dbfs) 0 sfdr (dbfs) 40 20 80 100 120 ?70 ?50 ?40 0 10 21521012 g56 60 ?80 ?60 ?30 ?20 ?10 dbfs dbc input level (dbfs) 10 0 snr (dbc and dbfs) 20 30 40 50 70 60 ?70 ?50 ?30 ?60 ?40 ?20 ?10 0 21521012 g57 dbfs dbc input frequency (mhz) 0 sfdr (dbfs) 50 40 60 70 800 21521012 g58 20 30 10 0 200 400 500 1000 90 80 600 100 300 900 700 input frequency (mhz) 0 snr (dbfs) 55 50 60 65 800 21521012 g59 45 40 200 400 500 1000 75 70 600 100 300 900 700 input frequency (mhz) ?5.0 input amplitude (dbfs) ?4.5 ?3.5 ?3.0 ?2.5 1000 ?0.5 21521012 g60 ?4.0 100 ?2.0 ?1.5 ?1.0 ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
13 for more information www.linear.com/ltc2152-12 pin functions v dd (pins 1, 2): 1.8 v analog power supply. bypass to ground with 0.1 f ceramic capacitor. pins 1, 2 can share a bypass capacitor. gnd (pins 3, 6, 10, 13, 35, exposed pad pin 41): adc power ground. the exposed pad must be soldered to the pcb ground. a in + (pin 4): positive differential analog input. a in C (pin 5): negative differential analog input. sense (pin 7): reference programming pin. connecting sense to v dd selects the internal reference and a 0.75v input range. an external reference between 1.2 v and 1.3v applied to sense selects an input range of 0.6 ? v sense . v ref (pin 8): reference voltage output. bypass to ground with a 2.2f ceramic capacitor. nominally 1.25v. v cm (pin 9): common mode bias output; nominally equal to 0.439?v dd . v cm should be used to bias the common mode of the analog inputs. bypass to ground with a 0.1f ceramic capacitor. enc + (pin 11): encode input. conversion starts on the rising edge. enc C (pin 12): encode complement input. conversion starts on the falling edge. nc (pins 16, 17): no connection. ov dd (pins 20, 30): 1.8 v output driver supply. bypass each pin to ground with separate 0.1 f ceramic capacitors. ognd (pin 21): lvds driver ground. sdo (pin 36): in serial programming mode, ( par / ser = 0v), sdo is the optional serial interface data output. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open- drain n-channel mosfet output that requires an external 2k pull-up resistor from 1.8 v to 3.3 v. if readback from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. sdi (pin 37): in serial programming mode , ( par / ser = 0 v), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in parallel programming mode ( par / ser = v dd ), sdi selects 3.5 ma or 1.75 ma lvds output current (see table 2). sck (pin 38): in serial programming mode, ( par / ser = 0 v), sck is the serial interface clock input. in parallel programming mode ( par / ser = v dd ), sck controls the sleep mode (see table 2). cs (pin 39): in serial programming mode, ( par / ser = 0v), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in parallel programming mode ( par / ser = v dd ), cs controls the clock duty cycle stabi- lizer (see t able 2). pa r / ser (pin 40): programming mode selection pin. connect to ground to enable the serial programming mode. cs , sck, sdi and sdo become a serial interface that control the a/d operating modes. connect to v dd to enable the parallel programming mode where cs , sck and sdi become parallel logic inputs that control a reduced set of the a/d operating modes. par / ser should be con - nected directly to ground or the v dd of the part and not be driven by a logic signal. 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
14 for more information www.linear.com/ltc2152-12 pin functions lvds outputs (ddr lvds) the following pins are differential lvds outputs. the output current level is programmable. there is an optional internal 100? termination resistor between the pins of each lvds output pair. d 0_1 C /d 0_1 + to d 10_11 C /d 10_11 + ( pins 18/19, 22/23, 24/25, 28/29, 31/32, 33/34): double-data rate digital outputs. two data bits are multiplexed onto each differential output pair. the even data bits ( d0, d2, d4, d6, d8, d10) appear when clkout + is low. the odd data bits ( d1, d3, d5, d7, d9, d11) appear when clkout + is high. clkout C /clkout + (pins 26/27): data output clock. the digital outputs normally transition at the same time as the falling and rising edges of clkout + . the phase of clkout + can also be delayed relative to the digital outputs by programming the mode control registers. of C /of + (pins 14/15): over/underflow digital output. of + is high when an overflow or underflow has occurred. this underflow is valid only when clkout + is low. in the second half clock cycle, the overflow is set to 0. functional block diagram figure 1. functional block diagram s/h v cm buffer buffer gnd v cm 0.1f correction logic output drivers 12-bit pipelined adc clock/duty cycle control 1.25v reference range select clock analog input 21521012 f01 ddr lvds v dd ov dd ognd cs spi v ref 2.2f gnd gnd sense sck sdi sdo par/ ser d10_11 ? ? ? d0_1 ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
15 for more information www.linear.com/ltc2152-12 timing diagrams double-data rate output timing, all outputs are differential lvds t h t c t d t l t skew d0 n-6 d1 n-6 d0 n-5 d1 n-5 d0 n-4 d1 n-4 d10 n-6 d11 n-6 d10 n-5 d11 n-5 d10 n-4 d11 n-4 of n-6 invalid of n-5 invalid of n-4 invalid t ap n + 1 n + 2 n + 3 n enc ? enc + d0_1 + d0_1 ? d10_11 + d10_11 ? clkout ? clkout + of + of ? 21521012 td01 ltm9003 a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 21521012 td02 cs sck sdi r/w sdo high impedance 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
16 for more information www.linear.com/ltc2152-12 converter operation the ltc2152-12/ltc2151-12/ltc2150-12 are 12- bit 250msps/210msps/170msps a/d converters that are powered by a single 1.8 v supply. the analog inputs must be driven differentially. the encode in - puts should be driven differentially for optimal per - formance. the digital outputs are double- data rate lvds. additional features can be chosen by programming the mode control registers through a serial spi port. analog input the analog input is a differential cmos sample-and-hold circuit (figure 2). it must be driven differentially around a common mode voltage set by the v cm output pin, which is nominally 0.439?v dd . the inputs should swing from v cm C 0.375 v to v cm + 0.375 v. there should be a 180 phase difference between the inputs. input drive circuits input filtering if possible, there should be an rc lowpass filter right at the analog inputs. this lowpass filter isolates the drive circuitry from the a/d sample- and- hold switching, and also limits wide band noise from the drive circuitry. figure 3 shows an example of an input rc filter. the rc compo - nent values should be chosen based on the applications input frequency. t ransformer-coupled circuits figure 3 shows the analog input being driven by an rf transformer with the common mode supplied through a pair of resistors via the v cm pin. at higher input frequencies a transmission line balun transformer (figures 4 and 5) has better balance, resulting in lower a/d distortion. figure 2. equivalent input circuit for differential input clock figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz applications information figure 4. recommended front-end circuit for input frequencies from 15mhz to 150mhz 2pf r on 20 r on 20 v dd v dd ltc2152-12 a in + 21521012 f02 2pf v dd a in ? enc ? enc + 2pf 2pf 1.2v 5 10k 5 25 25 4.7 4.7 10 0.1f 10pf 0.1f ltc2152-12 in 0.1f t1 1:1 t1: macom etc1-1t 21521012 f03 a in + a in ? v cm 10 0.1f 0.1f in 0.1f 0.1f t2 wbc1-1l t1 maba 007159- 000000 21521012 f04 ltc2152-12 a in + a in ? v cm 45 45 100 4.7 4.7 ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
17 for more information www.linear.com/ltc2152-12 applications information figure 5. recommended front-end circuit for input frequencies from 150mhz up to 900mhz figure 6. front-end circuit using a high speed differential amplifier amplifier circuits figure 6 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac-coupled to the a/d so the amplifiers output common mode voltage can be optimally set to minimize distortion. at very high frequencies an rf gain block will often have lower distortion than a differential amplifier. if the gain block is single-ended, then a transformer circuit (figures 3 and 5) should convert the signal to differential before driving the a/d. the a/d cannot be driven single-ended. reference the ltc2152-12/ltc2151-12/ltc2150-12 has an internal 1.25v voltage reference. for a 1.5 v input range with in - ternal reference , connect sense to v dd . for a 1.5 v input range with an external reference, apply a 1.25 v reference voltage to sense (figure 7). encode input the signal quality of the encode inputs strongly affects the a/d noise performance. the encode inputs should be treated as analog signalsdo not route them next to digital traces on the circuit board. the encode inputs are internally biased to 1.2 v through 10k equivalent resistance ( figure 8). if the common mode of the driver is within 1.1 v to 1.5 v, it is possible to drive figure 7. reference circuit figure 8. equivalent encode input circuit t1 45 45 10 4.7 0.1f 0.1f in 0.1f 0.1f t1: macom etc1-1-13 21521012 f05 ltc2152-12 a in + a in ? v cm 4.7 maba 007159- 000000 100 4.7 4.7 50 50 0.1f a in + a in ? 0.1f 3pf 3pf v cm ltc2152-12 21521012 f06 input 0.1f 3pf scaler/ buffer 1.25v sense v ref 21521012 f07 5 adc reference sense detector 2.2f v dd ltc2152-12 21521012 f08 1.2v 10k 10k enc + enc ? 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
18 for more information www.linear.com/ltc2152-12 applications information the encode inputs directly. otherwise, a transformer or coupling capacitors are needed ( figures 9 and 10). the maximum ( peak) voltage of the input signal should never exceed v dd + 0.1v or go below C0.1v. clock duty cycle stabilizer for good performance the encode signal should have a 50% (5%) duty cycle. if the optional clock duty cycle stabilizer circuit is enabled, the encode duty cycle can vary from 30% to 70% and the duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the encode signal changes frequency or is turned off, the duty cycle stabilizer circuit requires one hundred clock cycles to lock onto the input clock. the duty cycle stabilizer is enabled via spi register a 2 ( see spi control register) or by cs in parallel programming mode. figure 9. sinusoidal encode drive for applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. if the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. digital outputs the digital outputs are double-data rate lvds signals. two data bits are multiplexed and output on each differential output pair. there are six lvds output pairs (d0_1 + / d0_1 C through d10_11 C /d10_11 + ). overflow (of + /of C ) and the data output clock (clkout + /clkout C ) each have an lvds output pair. by default the outputs are standard lvds levels : 3.5ma output current and a 1.25 v output common mode voltage. figure 10. pecl or lvds encode drive ltc2152-12 t1 v dd 21521012 f09 1.2v 10k 10k 50 100 50 0.1f 0.1f 0.1f t1: macom etc1-1-13 v dd ltc2152-12 pecl or lvds input 21521012 f10 1.2v 10k 10k 100 0.1f 0.1f enc + enc ? ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
19 for more information www.linear.com/ltc2152-12 applications information an external 100 differential termination resistor is re- quired for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd and ognd, which are isolated from the a/d core power and ground. programmable lvds output current the default output driver current is 3.5 ma. this current can be adjusted by serially programming mode control register a 3 ( see table 3). available current levels are 1.75ma, 2.1ma, 2.5ma, 3ma, 3.5ma, 4ma and 4.5ma. optional lvds driver internal termination in most cases, using just an external 100? termination resistor will give excellent lvds signal integrity. in ad - dition, an optional internal 100? termination resistor can be enabled by serially programming mode control register a 3. the internal termination helps absorb any reflections caused by imperfect termination at the re - ceiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. overflow bit the overflow output bit ( of) outputs a logic high when the analog input is either overranged or underranged. the overflow bit has the same pipeline latency as the data bits. when clkinv is set to 0 in the spi register a2, of signal is valid when clkout + is low as shown in the timing diagram. phase shifting the output clock to allow adequate setup and hold time when latching the output data, the clkout + signal may need to be phase shifted relative to the data output bits. most fpgas have this feature; this is generally the best place to adjust the timing. alternatively, the adc can also phase shift the clkout + / clkout C signals by serially programming mode control register a2. the output clock can be shifted by 0, 45, 90, or 135. to use the phase shifting feature, the clock duty cycle stabilizer must be turned on. another con - trol register bit can invert the polarity of clkout + and clkout C , independently of the phase shift. the combina- tion of these two features enables phase shifts of 45 up to 315 (figure 11). 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
20 for more information www.linear.com/ltc2152-12 applications information figure 11. phase-shifting clkout clkout + d0-d11, of phase shift 0 45 90 135 180 225 270 315 clkinv 0 0 0 0 1 1 1 1 clkphase1 mode control bits 0 0 1 1 0 0 1 1 clkphase0 0 1 0 1 0 1 0 1 21521012 f11 enc + ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
21 for more information www.linear.com/ltc2152-12 figure 12. functional equivalent of digital output randomizer figure 13. unrandomizing for randomized digital output signal applications information d ata format table 1 shows the relationship between the analog input voltage, the digital data output bits and the overflow bit. by default the output data format is offset binary. the 2 s complement format can be selected by serially program - ming mode control register a4. table 1. output codes vs input voltage a in + C a in C (1.5v range) of d 11-d0 (offset binar y) d11-d0 (2s complement) >0.75v +0.75v +0.7496337v 1 0 0 1111 1111 1111 1111 1111 1111 1111 1111 1110 0111 1111 1111 0111 1111 1111 0111 1111 1110 +0.0003662v +0.000000v C0.0003662v C0.0007324v 0 0 0 0 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 C0.74963378v C0.75v < C0.75v 0 0 1 0000 0000 0001 0000 0000 0000 0000 0000 0000 1000 0000 0001 1000 0000 0000 1000 0000 0000 digital output randomizer interference from the a/d digital outputs is sometimes unavoidable. digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off-chip, these unwanted tones can be randomized, which reduces the unwanted tone amplitude. the digital output is randomized by applying an exclu - sive - or logic operation between the lsb and all other data output bits. to decode, the reverse operation is appliedan exclusive -or operation is applied between the lsb and all other bits. the lsb, of and clkout out- puts are not affected. the output randomizer is enabled by serially programming mode control register a4. clkout clkout of d11/d0 d10/d0 ? ? ? d1/d0 d0 21521012 f12 of d11 d10 d1 d0 randomizer on d11 fpga pc board d10 ? ? ? d1 d0 21521012 f13 d0 d1/d0 d10/d0 d11/d0 of clkout ltc215x-12 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
22 for more information www.linear.com/ltc2152-12 alternate bit polarity another feature that may reduce digital feedback on the circuit board is the alternate bit polarity mode. when this mode is enabled, all of the odd bits ( d1, d3, d5, d7, d9, d11) are inverted before the output buffers. the even bits ( d0, d2, d4, d6, d8, d10), of and clkout are not affected. this can reduce digital currents in the circuit board ground plane and reduce digital noise, particularly for very small analog input signals. the digital output is decoded at the receiver by inverting the odd bits ( d1, d3, d5, d7, d9, d11). the alternate bit polarity mode is independent of the digital output random - izereither both or neither function can be on at the same time. the alternate bit polarity mode is enabled by serially programming mode control register a4. digital output test patterns to allow in-circuit testing of the digital interface to the a/d, there are several test modes ( activate by setting dteston) that force the a/d data outputs ( of, d11 to d0) to known values: all 1s: all outputs are 1 all 0s: all outputs are 0 alternating: outputs change from all 1 s to all 0 s on alternating samples checkerboard: outputs change from 1010101010101 to 0101010101010 on alternating samples. the digital output test patterns are enabled by serially programming mode control register a4. when enabled, the test patterns override all other formatting modes: 2s complement, randomizer, alternate-bit polarity. output disable the digital outputs may be disabled by serially program - ming mode control register a3. all digital outputs, includ- ing of and clkout, are disabled. the high impedance disabled state is intended for long periods of inactivity, it is not designed for multiplexing the data bus between multiple converters. sleep mode the a/d may be placed in a power-down mode to conserve power. in sleep mode, the entire a/d converter is powered down, resulting in < 2 mw power consumption. if the en - code input signal is not disabled, the power consumption will be higher ( up to 2 mw at 250 msps). sleep mode is enabled by mode control register a 1 ( serial programming mode), or by sck (parallel programming mode). the amount of time required to recover from sleep mode depends on the size of the bypass capacitors on v ref . for the suggested values in figure 1, the a/d will stabi- lize after 0.1 ms + 2500 ? t p where t p is the period of the sampling clock. nap mode in nap mode the a/d core is powered down while the internal reference circuits stay active, allowing faster wakeup. recovering from nap mode requires at least 100 clock cycles. wake-up time from nap mode is guaranteed only if the clock is kept running, otherwise sleep mode, wake-up time conditions apply. nap mode is enabled by setting register a1 in the serial programming mode. device programming modes the operating modes of the ltc215x-12 can be pro - grammed by either a parallel interface or a simple serial inter face. the serial interface has more flexibility and can program all available modes. the parallel interface is more limited and can only program some of the more commonly used modes. parallel programming mode to use the parallel programming mode, par / ser should be tied to v dd . the cs , sck and sdi pins are binary logic inputs that set certain operating modes. these pins can be tied to v dd or ground, or driven by 1.8v, 2.5 v, or 3.3v cmos logic. table 2 shows the modes set by cs , sck and sdi. applications information ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
23 for more information www.linear.com/ltc2152-12 table 2. parallel programming mode control bits) pin description cs clock duty cycle stabilizer control bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on sck power-down control bit 0 = normal operation 1 = sleep mode (entire adc is powered down) sdi lvds current selection bit 0 = 3.5ma l vds current mode 1 = 1.75ma l vds current mode serial programming mode to use the serial programming mode, par / ser should be tied to ground. the cs , sck, sdi and sdo pins become a serial interface that program the a/d control registers. data is written to a register with a 16- bit serial word. data can also be read back from a register to verify its contents. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the first sixteen rising edges of sck. any sck rising edges after the first sixteen are ignored. the data transfer ends when cs is taken high again. the first bit of the 16- bit input word is the r/w bit. the next seven bits are the address of the register (a6:a0). the final eight bits are the register data (d7:d0). if the r/ w bit is low, the serial data ( d7:d0) will be writ- ten to the register set by the address bits ( a6:a0). if the r/ w bit is high, data in the register set by the address bits (a6:a0) will be read back on the sdo pin ( see the timing diagrams). during a readback command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground with a 200? impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and readback is not needed, then sdo can be left floating and no pull-up resistor is needed. table 3 shows a map of the mode control registers. software reset if serial programming is used, the mode control registers should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset it is neces - sary to write 1 in register a 0 ( bit d7). after the reset is complete, bit d7 is automatically set back to zero. this register is write-only. grounding and bypassing the ltc215x-12 requires a printed circuit board with a clean unbroken ground plane in the first layer beneath the adc. a multilayer board with an internal ground plane is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. high quality ceramic bypass capacitors should be used at the v dd , ov dd , v cm and v ref pins. bypass capacitors must be located as close to the pins as possible. size 0402 ceramic capacitors are recommended. the traces connecting the pins and bypass capacitors must be kept short and should be made as wide as possible. the analog inputs, encode signals and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. heat transfer most of the heat generated by the ltc215x-12 is trans - ferred from the die through the bottom-side exposed pad and package leads onto the printed circuit board. for good electrical and thermal performance, the exposed pad must be soldered to a large grounded pad on the pc board. this pad should be connected to the internal ground planes by an array of vias. applications information 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
24 for more information www.linear.com/ltc2152-12 applications information table 3. serial programming mode register map ( par /ser = gnd). an x indicates an unused bit. register a0: reset register (address 00h) write-only d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h. this bit is automatically set back to zero after the reset is complete. bits 6-0 unused bit. register a1: power-down register (address 01h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x sleep nap 0 0 bits 7-4 unused, these bits are read back as 0. bit 3 sleep 0 = normal operation 1 = power down entire adc bit 2 nap 0 = normal mode 1 = low power mode bit 1-0 must be set to 0. register a2: timing register (address 02h) d7 d6 d5 d4 d3 d2 d1 d0 x x x x clkinv clkphase1 clkphase0 dcs bits 7-4 unused, these bits are read back as 0. bit 3 clkinv output clock invert bit 0 = normal clkout polarity (as shown in the timing diagrams) 1 = inverted clkout polarity bits 2-1 clkphase1:clkphase0 output clock phase delay bits 00 = no clkout delay (as shown in the timing diagrams) 01 = clkout + /clkout C delayed by 45 (clock period ? 1/8) 10 = clkout + /clkout C delayed by 90 (clock period ? 1/4) 11 = clkout + /clkout C delayed by 135 (clock period ? 3/8) note: if the clkout phase delay feature is used, the clock duty cycle stabilizer must also be turned on. bit 0 dcs clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer off 1 = clock duty cycle stabilizer on ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
25 for more information www.linear.com/ltc2152-12 register a3: output mode register (address 03h) d7 d6 d5 d4 d3 d2 d1 d0 x x x ilvds2 ilvds1 ilvds0 termon outoff bits 7-5 unused, these bits are read back as 0. bits 4-2 ilvds2:ilvds0 lvds output current bits 000 = 3.5ma lvds output driver current 001 = 4.0ma lvds output driver current 010 = 4.5ma lvds output driver current 011 = not used 100 = 3.0ma lvds output driver current 101 = 2.5ma lvds output driver current 110 = 2.1ma lvds output driver current 111 = 1.75ma lvds output driver current bit 1 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2 the current set by ilvds2:ilvds0 bit 0 outoff digital output mode control bits 0 = lvds ddr 1 = lvds tristate (high impedance) register a4: d ata format register (address 04h) d7 d6 d5 d4 d3 d2 d1 d0 outtest2 outtest1 outtest0 abp 0 dteston rand twoscomp bits 7-5 outtest2:outtest0 digital output test pattern bits 000 = all digital outputs = 0 001 = all digital outputs = 1 010 = alternating output pattern. of, d11-d0 alternate between 00000 0000 0000 and 11111 1111 1111 100 = checkerboard output pattern. of, d11-d0 alternate between 01010 1010 1010 and 10101 0101 0101 bit 4 abp alternate bit polarity mode control bit 0 = alternate bit polarity mode off 1 = alternate bit polarity mode on bit 3 must be set to 0. bit 2 dteston enable digital patterns (bits 7-5) 0 = normal mode 1 = enable the digital output t est patterns bit 1 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on bit 0 t woscomp tw o s complement mode control bit 0 = offset binary data format 1 = tw o s complement data format applications information 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
26 for more information www.linear.com/ltc2152-12 applications information silkscreen top inner layer 1 inner layer 2 inner layer 3 215210 f14 215210 f15 215210 f16 215210 f17 bottom layer inner layer 5 inner layer 4 215210 f18 215210 f19 215210 f20 ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
27 for more information www.linear.com/ltc2152-12 typical applications ltc2152-12 1 2 3 4 5 6 7 8 9 10 41 v dd 40 39 38 37 36 35 34 33 32 31 par/ser cs sck sdi sdo gnd d10_11 + d10_11 ? d8_9 + d8_9 ? d10_11 + d10_11 ? d8_9 + d8_9 ? 11 12 13 14 15 16 17 18 19 20 clk + clk ? gnd of ? of + nc nc d0_1 ? d0_1 + ov dd 30 29 28 27 26 25 24 23 22 21 ov dd d6_7 + d6_7 ? clkout + clkout ? d4_5 + d4_5 ? d2_3 + d2_3 ? ognd d6_7 + d6_7 ? clkout + clkout ? d4_5 + d4_5 ? d2_3 + d2_3 ? 21521012 ta02 sense sense tp3 r9, 1k c21 0.1f vcm c16 2.2f c13 2.2f r19 10 10 r14 10 r16 100 v dd v dd gnd a ina + a ina ? gnd sense v ref v cm gnd gnd a ina + a ina ? sdo sdi sck cs par/ser 0.1f 0.1f 100 clk + clk ? of ? of + nc nc d0_1 ? d0_1 + 0.2f 0.1f 0.1f ltc2152-12 schematic 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
28 for more information www.linear.com/ltc2152-12 package description uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?) 6.00 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 45 chamfer 0.40 0.10 4039 1 2 bottom view?exposed pad 4.50 ref (4-sides) 4.42 0.10 4.42 0.10 4.42 0.05 4.42 0.05 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.50 0.05 (4 sides) 5.10 0.05 6.50 0.05 0.25 0.05 0.50 bsc package outline r = 0.10 typ please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa
29 for more information www.linear.com/ltc2152-12 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 12/14 changed pipeline latency to 6 updated g17, g37 and g57 5 and 15 7, 10 and 12 21521012fa ltc2152-12/ ltc2151-12/ltc2150-12
30 for more information www.linear.com/ltc2152-12 ? linear technology corporation 2011 lt1214 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc2152-12 related parts part number description comments adcs ltc2208 16-bit, 130msps, 3.3v adc, lvds outputs 1250mw, 77.7db snr, 100db sfdr, 64-lead qfn package ltc2157-14/ltc2156-14/ ltc2155-14 14-bit, 250msps/210msps/170msps, 1.8v dual adc, ddr lvds outputs 650 mw/616mw/567mw, 70db snr, 90db sfdr, 64-lead qfn package ltc2152-14/ltc2151-14/ ltc2150-14 14-bit, 250msps/210msps/170msps, 1.8v dual adc, ddr l vds outputs 356mw/338mw/313mw, 70db snr, 90db sfdr, 40-lead qfn package ltc2262-14 14-bit, 150msps 1.8v adc, ultralow power 149mw, 72.8db snr, 88db sfdr, ddr lvds/ddr cmos/cmos outputs, 40-lead qfn package rf mixers/demodulators lt ? 5517 40mhz to 900mhz direct conversion quadrature demodulator high iip3: 21dbm at 800mhz, integrated lo quadrature generator lt5527 400mhz to 3.7ghz high linearity downconverting mixer 24.5dbm iip3 at 900mhz, 23.5dbm iip3 at 3.5ghz, nf = 12.5db, 50 single-ended rf and lo ports lt 5575 800mhz to 2.7ghz direct conversion quadrature demodulator high iip3: 28dbm at 900mhz, integrated lo quadrature generator, integrated rf and lo transformer amplifiers/filters ltc6409 10ghz gbw, 1.1nv/ hz differential amplifier/ adc driver 88db sfdr at 100mhz, input range includes ground 52ma supply current, 3mm 2mm qfn package ltc6412 800mhz, 31db range, analog-controlled variable gain amplifier continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm 4mm qfn-24 package ltc 6420-20 1.8ghz dual low noise, low distortion differential adc drivers for 300mhz if fixed gain 10v/v, 1nv/ hz total input noise, 80ma supply current per amplifier, 3mm 4mm qfn-20 package receiver subsystems lt m ? 9002 14-bit dual channel if/baseband receiver subsystem integrated high speed adc, passive filters and fixed gain differential amplifiers ltm9003 12-bit digital pre-distortion receiver integrated 12-bit adc down-converter mixer with 0.4ghz to 3.8ghz input frequency range ltc2152-12: 32k point 2-tone fft , f in = 71mhz and 69mhz, 250msps typical application frequency (mhz) 0 ?120 amplitude (dbfs) ?100 ?80 ?60 ?40 0 20 40 60 80 21521012 ta03b 100 120 ?20 s/h correction logic output drivers 12-bit pipelined adc clock/duty cycle control d10_11 ? ? ? d0_1 clock analog input 21521012 ta03a ddr lvds v dd gnd ov dd ognd ltc2152-12/ ltc2151-12/ltc2150-12 21521012fa

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